This invention relates to data processing systems which include computing devices, and addressable memory systems that utilize a plurality of memory modules. More particularly, it relates to a data processing system that utilizes an addressable memory system comprised of a plurality of physically discrete memory modules, one or more of which may be absent from the system at any, particular time. Further it relates to a memory address assignment system that automatically assigns sequential module addresses to available modules available in the physical array, thereby bypassing missing memory modules in the addressing system.
In data processing systems it has long been recognized that it is desirable to provide large capacity memory systems arranged for storing and reading data from addressable locations. It is common to physically construct the memory systems in discrete modules that are alternatively referred to as arrays, panels, and the like. In binary systems it is common for each module to be physically constructed to accommodate a predetermined number of addressable locations. These arrangements are such that in the total addressing sequence, there is a portion of the address that designates the module and another portion of the address that designates the specific memory location within the module. For example, a memory module that is arranged to store 4,096 addressable locations can be addressed discretely to each addressable location by an octal address range from 0000 through 7777, thereby yielding octal 10000 sequential addresses. As is well known, this readily translates to binary discrete addressing. If a system capacity larger than a single module is desired, it is necessary only to add addressing designations that select additional modules discretely in addition to the specific addressing within the module.
In a memory system utilizing a plurality of modules, it is well known to provide a physical structure that provides for the mechanical support of each of the modules,together with electrical interconnection that provides power for each of the modules, and circuit interconnections that permit accessing each of the memory modules. In prior art systems, it was common for the physical location of a memory module to provide a part of the addressing selection within the system. The arrangements were such that the physical location afforded a position in the sequential addressing system that related to multiples of the module capacity. For example, a first module position would relate to the lowest ordered sequence of addresses that would extend from 0 through the capacity of the module. Once the sequential addressing extended beyond the capacity of first module, there would be automatic switching to the next physical location where sequential addressing would continue through the capacity of the second module. This sequential addressing would then continue through the number of modules available in the system. Systems of this type were firmly arranged for sequential addressing. Where a portion of the addressing was dependent upon physical location, it led to the problem of addressing gaps in the event a particular module or modules were inoperative for any reason. In other words, an inoperative or absent module in such a system would provide a gap of addressable locations equal to the capacity of the missing module. Since programs are characteristically generated and operate with the concept of available sequential addressing, complex procedures would be required to accommodate missing modules. Modules can be missing from the system because they are physically removed for maintenance, inspection, or repair, or can be physically present but switched out of the system because they have been found to be subject to malfunction. It can be seen, then, that systems designed to utilize sequentially addressable memory locations can be effectively rendered inoperable if one of the memory modules is removed or switched off for malfunction unless a procedure is provided that allows for the degraded system operation by re-assigning the effective sequencing of those memory modules that are available.